Checked against the fab
Stackup, fab rules, vias and net classes with impedance and current targets, so a track that is too narrow is reported with the width that fixes it.
ToolsDesign
agentee
Electronics design in plain TOML
Boards, schematics, layouts and simulations are TOML files that you or a coding agent write. agentee checks every edit against the fab, draws the board, and lets you place parts and route tracks by hand in the same files.
- Latest
- 0.3.0
- Released
- 12 Oct 2026
- Licence
- GPL-3.0-or-later
What it does
Simulated on the GPU
FDTD for RF layouts with S-parameters out, cascade, channel and PDN analysis, DC drop, thermal, and circuit and logic simulation of the schematic.
KiCad parts
Symbols and footprints import from the KiCad libraries, so a part rarely has to be drawn by hand.
Ready for the fab
Writes Gerbers, drill files, a BOM and placement, and exports the board with its part models as one STEP for the case.
Works with
KiCad librariesGerberExcellonSTEPMCP
Opens
.board.toml.sch.toml.pcb.toml.sym.toml.fp.toml.sim.toml
Drop one of these on the Bench Suite window and it opens here.
